A common requirement of current integrated circuit manufacturing and packaging is the use of interposers to receive single or multiple integrated circuit dies. The use of through vias or through substrate vias (“TSVs”) extending through the interposers is increasing. These through vias allow electrical coupling between integrated circuit dies and components mounted on one side of an interposer, and terminals such as solder balls mounted on the opposite side of the interposer. Further, the use of TSV technologies with silicon interposer substrates enable wafer level processing (“WLP”) of the interposer assemblies. This technique is increasingly applicable to increasing memory or storage device density, for example, without added circuit board area. As demand for hand held and portable devices such as smart phones and tablet computers increases, board area and board size restrictions also increases, and the use of the interposer assemblies and TSVs can meet these requirements. Vertically stacking of components using TSV technologies is referred to as “3DIC” and is increasingly used in developing advanced integrated systems.
During processing of the interposer, a typical approach is to perform a reactive ion etch (“RIE”) process on a wafer. Often the wafer is a silicon wafer with, or without, active devices formed on it, and the etch process forms TSVs. The TSVs are very deep when compared to vias and contacts used in the conventional semiconductor processing for metal interconnection, for example. Also, the TSVs are typically formed into and through silicon or semiconductor substrates, while traditional vias and contacts are formed in dielectric materials such as nitrides, oxides, and the like. The use of wafers as an interposer enables wafer level processing (“WLP”) of 3DIC structures which may include flip chip or wire bonded mounted integrated circuits on one side of the interposer, and solder ball or solder column connections on the back side for board level connections; this approach may be combined with a wafer dicing step performed late in the process, to form multiple 3DIC assemblies on a single wafer substrate prior to separating the assemblies.
Because of the high aspect ratios of the deep via holes formed using RIE processes for TSVs on wafers, additional techniques have been developed called deep RIE or “DRIE”. The DRIE process is performed in a machine tool that includes a wafer handling system, a wafer station or platen within a vacuum chamber, reactive gas inlets, and electrodes for coupling an RF energy source. A wafer is processed by placing the wafer on a platen in the chamber, creating a vacuum, introducing certain gases, and initiating a plasma using the RF energy. Ions are accelerated and bombarded against the wafer. In DRIE chemical etching may be combined with physical bombardment of ion etching to further increase the etch rate achieved. Patterning is performed using masks over the wafer and photolithography is performed to define the via locations. The ions etch and sputter away the silicon in the exposed regions to form the vias. The vias are typically formed as “blind” vias from one side of the wafer, typically the DRIE etch is done from the “top” or “die side” of the wafer. After many processing steps this wafer will become the substrate or 3DIC interposer. Once the vias are etched by the DRIE process, the TSVs are then processed in an electroless or electroplating process to fill the vias with conductive material, typically copper. Later the backside of the wafer is partially removed in a thinning step, using chemical and mechanical grinding processes, to expose the bottom of the vias and thus complete the TSVs which extend through the interposer wafer.
The TSVs are essentially high aspect ratio, vertical holes. To achieve this profile, the use of a highly anisotropic process is needed. The DRIE process uses two alternating operations, an RIE etch, and deposition of an inert passivation layer. By alternatively etching and depositing, the via holes can be made deeper while the via sides remain vertical due to the presence of the protective passivation material. These etch and deposition processes are alternatively performed until the deep through via holes are completed. These vias may be up to 100 microns or more deep, and thus, the aspect ratio of the vias may be greater than or equal to 20:1 for example.
In order to control this TSV etch process, known methods typically process monitor or test wafers and observe the resulting via depths against a processing time. A recipe is developed that compares the depth of the TSVs in the monitor wafers to the time of DRIE etching, and a selected time is chosen.
However the use of the monitor wafer as an RIE etch endpoint determination is not accurate. Significant yield problems have been observed due to lot-to-lot, run-to-run, and even wafer-to-wafer variations in the resulting TSV depths. Some of these variations may be addressed by rework, adding cost to the interposer and the 3DIC process, other variations in TSV depth may be so great as to cause scrapped wafers. These problems lower yield, increase costs, and increase production time resulting in lowered throughput.
A continuing need thus exists for methods and systems to efficiently perform RIE etching with a reliable endpoint detection to achieve robust and uniform TSV depths, without the problems and costs experienced when using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.